The disclosed embodiments of the present invention relate to chip area reduction, and more particularly, to a shared radio-frequency (RF) architecture of a receiver front-end supporting multiple wireless communication standards.
Both wireless fidelity (Wi-Fi) and Bluetooth (BT) operate in the free 2.4 GHz Industrial, Scientific and Medical (ISM) band; it is generally acknowledged that Wi-Fi and Bluetooth are two of the most widely used wireless technologies in consumer electronic devices. As a result, more and more handheld devices are being shipped with both Wi-Fi and Bluetooth functionalities.
Using separated Wi-Fi and Bluetooth dies on one embedded device, however, will increase cost, chip area and pin count. Although some solutions have been proposed to co-locate Wi-Fi and Bluetooth functional blocks in one integrated chip in order to lower the cost, these solutions do not address the problem of reducing chip area and pin count. Please refer to FIG. 1, which is a block diagram illustrating a traditional architecture of a dual-mode (Wi-Fi and Bluetooth) front-end 100. The dual-mode front-end 100 includes a Wi-Fi module 120 and a BT module 140. The Wi-Fi module 120 includes a Wi-Fi receiver (RX) front-end 122, a Wi-Fi transmitter (TX) front-end 124 and a Wi-Fi intermediate frequency (IF) circuit 126. The BT module 140 includes a BT RX front-end 142, a BT TX front-end 144 and a BT IF circuit 146. As illustrated in FIG. 1, the Wi-Fi RX front-end 122 and the BT RX front-end 142 are separated from each other, and therefore have their own mixer, synthesizer, local oscillation (LO) generator, etc.
There is a need, therefore, for a shared radio-frequency (RF) architecture of a receiver front-end which can support multiple wireless communication standards to reduce chip area.